In most modern electronic devices activities inside the integrated circuits are coordinated by on-chip clock signals of various frequencies. This is especially true for large System-on-Chip (SoC) integrated circuits where large numbers of functions are integrated inside a single chip and each function has its unique clock frequency requirement. The on-chip frequencies are usually generated by Phase Lock Loop (PLL). The PLLs is the heart of the integrated circuit controlling all operations. PLLs have known disadvantages. The frequencies synthesisable by PLLs are limited. PLLs have high design complexity including heavy analog content. PLLs have response speed that is not instantaneous.
Flying-Adder architecture is a novel technique for generating clock signals on an integrated circuit. This architecture can solve many difficult problems in various commercial projects. The character of this architecture can be summarized as a circuit level enabler which enables system level innovations.
The information is collected through the sensors which converts the real world physical phenomena generally into voltage or current. An analog-to-digital converter (ADC) is employed to transfer the information into digital format for processing. After processing, the signal is converted back to voltage or current via a digital-to-analog converter (DAC) to control the real world activities. In this approach, the magnitude of the signal in voltage or current is the information. ADC and DAC are used to quantify the information. Many real world phenomena are more naturally suitable for rate of switching representation. Using this representation requires a frequency-to-digital converter (FDC) and a digital-to-frequency converter (DFC). A FDC is easily constructed using known techniques. This invention provides a circuit level enabler for a DFC.